The present invention generally relates to semiconductor manufacturing, and, more particularly to processes for fabricating a network of nanometric lines made of single-crystal silicon on an insulating substrate.
A network of lines made of single-crystal silicon on an insulating substrate may be a very promising structure for applications in the fabrication of transistors, memories, optoelectronic devices and others. A network of lines made of single-crystal silicon on an insulating substrate may be obtained, of course, by photolithography and etching of a substrate of the SOI (silicon on insulator) type. However, this approach can only provide lines and interline spacings within the resolution limit of the photolithography process. Photolithography processes provide, at the very best, lines having a width of 100 nanometers or more to be obtained.
It would therefore be desirable to have available a process for making lines made of single-crystal silicon of very small width, in particular less than 100 nanometers, to be obtained, so as to increase the integration of the devices obtained and also to promote mechanical and optoelectronic transport effects.
A feature of the present invention is therefore a process for fabricating a network of nanometric lines made of single-crystal silicon on an insulating substrate, and in particular of parallel nanometric lines of a width less than 100 nanometers.
According to the invention, the process for fabricating a network of nanometric lines made of single-crystal silicon on an insulating substrate includes: (a) the production of a substrate comprising a single-crystal silicon body, a lateral isolation defining a central part in the body, a recess formed in the central part having a bottom wall made of dielectric material, preferably SiO2, a first pair of opposed parallel sidewalls made of dielectric material, preferably SiO2, and a second pair of opposed parallel sidewalls, at least one of the sidewalls of the second pair being formed from single-crystal silicon; (b) the epitaxial growth in the recess, from the sidewall made of single-crystal silicon of the recess, of an alternating network of parallel lines made of single-crystal SiGe alloy and of single-crystal silicon; and (c) the etching of the lines made of single-crystal SiGe alloy, to form in the recess a network of parallel lines made of single-crystal silicon insulated from each other.
Use of the epitaxial growth technique to construct the lines of the structure according to the invention makes it possible to chose, virtually as required, the fineness of the lines. Furthermore, the use of the etching selectivity between the SiGe alloy and silicon allows the network of single-crystal silicon lines to be constructed on the insulating substrate having well-defined dimensions and virtually any fineness required by the designer.
Another major advantage of the process of the invention is that it can be implemented either from a solid single-crystal silicon substrate or from a conventional so-called SOI (Silicon On Insulator) substrate.
In an alternative embodiment of the invention, the opposed parallel sidewalls of the second pair of sidewalls of the recess formed in the central part of the silicon body of the substrate are formed by single-crystal silicon and the epitaxial growth of the alternating network of parallel lines made of single-crystal SiGe alloy and of lines made of single-crystal silicon is carried out from these two opposed parallel sidewalls.
Preferably, the width (fineness) of the alternating lines of the network is from 5 to 20 nanometers.
Because of the use of epitaxial growth to form the network of alternating lines, it is possible to choose, as required, the periodicity of the lines made of single-crystal silicon and of the interline spaces, as well as their width. However, care should be taken not to exceed the critical thicknesses (known to those skilled in the art), to avoid the risk of impairing the stress relaxation of the layers.
In a first embodiment of the invention, the substrate of step (a) is obtained from a solid substrate made of single-crystal silicon comprising a lateral isolation defining a central part of the solid substrate; masking and etching of the central part to form therein a recess having a bottom wall, a first pair of opposed parallel sidewalls made of dielectric material and a second pair of opposed parallel sidewalls, at least one of the walls of which is formed by single-crystal silicon; treatment of the bottom wall of the recess to increase the silicon oxidation rate therein; formation, on the bottom wall and the opposed parallel sidewalls of the second pair, of a silicon oxide layer which is thicker on the bottom wall than on the opposed sidewalls; and isotropic etching of the silicon oxide in order to remove the silicon oxide layer from the opposed parallel sidewalls of the second pair, while leaving a silicon oxide layer on the bottom wall of the recess.
In a second embodiment of the invention, the substrate of step (a) is obtained from a so-called SOI substrate including: a stack of a lower layer made of single-crystal silicon, a silicon oxide interlayer and an upper layer comprising a central part made of single-crystal silicon bounded by a lateral isolation; the formation on the upper layer of a thin silicon oxide layer; the formation on the thin silicon oxide layer of a mask; the etching through the mask of the thin silicon oxide layer and of the central part of the upper layer of the SOI substrate, stopping on the silicon oxide interlayer, so as to form a recess having a bottom wall made of silicon oxide, a first pair of opposed parallel sidewalls made of dielectric material and a second pair of opposed parallel sidewalls, at least one of which is formed from single-crystal silicon; and the removal of the mask.
Preferably, the opposed parallel sidewalls made of dielectric material of the first pair of sidewalls are formed by walls of the lateral isolation, generally made of silicon oxide (SiO2) Preferably, when one of the sidewalls of the second pair of sidewalls is not made of single-crystal silicon, this sidewall is formed by a wall of the lateral isolation, generally made of silicon oxide (SiO2).
The present invention also relates to a device comprising a substrate having a single-crystal silicon body and a lateral isolation defining in the body a central part. The central part comprises a recess. This device includes, in the recess, a network of parallel lines made of single-crystal silicon, which lines are spaced apart and insulated from each other. Preferably, these single-crystal silicon lines lie on a bottom wall, made of dielectric material such as SiO2, of the recess. Preferably, also, the single-crystal silicon lines are buried with respect to the upper surface of the single-crystal silicon body, i.e. the upper surfaces of these lines lie in the plane of the upper surface of the single-crystal silicon body or below this surface.
The spaces between the single-crystal silicon lines may be formed from a gaseous dielectric material such as air or from a solid dielectric material such as, for example, SiO2 or Si3N4. The width of the single-crystal silicon lines and of the interline spaces is generally from 5 to 20 nanometers.